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The digital pattern generator DPG1 is intended to drive up to 25 digital channels as a pulse sequencer, driven by external input signals like photon counters or the like. It is driven by a state engine of up to 512 states which can make conditional jumps depending on the state of external inputs, the state of counters scaling external inputs, loop counters, and software hooks.
Each step lasts an integer multiple of 10ns. The target application is pulse control of small or medium scale quantum information processing systems. A typical application requires e.g. a particular sequence to load an atom into a trap, checks if there is sufficient fluorescence to determine its presence, and switches to a measurement sequence. Relatively complex pulse sequences can be programmed with very few steps.
The device features 3 rows of 8 digital outputs, which can be either TTL-compatible levels for 50 Ohm transmission lines, or negative NIM signals through different daughter boards. The four input lines accept either NIM or TTL level signals, and are suitable to detect photodetector events or other digital input lines. The main board has an additional output and a frequency reference input.
The device is a modular unit to be powered by a Eurocard rack system (sold separately) and does not require a driver to operate, the host and device communicate only by a serial interface.
State Engine:
| 512 states with a variable duration of 1 to 65536 elementary time steps of 10ns and conditional branching to other states |
Signal Inputs:
| Impedance | 50Ohm |
| Input standards | TTL or NIM signal standard (software selectable) |
| Connector | LEMO00 size coaxial connector (optional: SMA) |
Input Processing:
| Loadable 16 bit wide counters that can be decremented by hardware input lines maximum counting frequency >200MHz range |
Output:
| 3 Banks of 8 outputs either TTL or NIM standard, one additional LEMO00/NIM |
Nim Output Bank:
| Connector | LEMO00 size coaxial connectors for 50 Ohm impedence cables |
| Low | 0V |
| High | <-800mV into lines terminated with 50 Ohm into ground |
| Transition time | 10%-90% <1.5ns |
TTL Output Bank:
| Connector | BNC 50 Ohm impedence, series-terminated on transmitter side (leave receiver at high impedance) |
| Low | 0V |
| High | >1.6V into open end of 50Ohm cable |
| Transition time | 10%-90% TBD |
Clock Reference:
| External reference frequency | 10MHz nominal (accepts 9...11MHz) to seed internal 100MHz PLL or any frequency <110MHz for use as direct clock |
| External reference amplitude | 150mVpp min, 2.3Vpp max |
| Clock selection | automatic or forced manual |
| Internal clock accuracy | <20ppm, temperature drift TBD |
Interface:
| Host connection | USB CDC ACM class / virtual com port (no device driver necessary) |
| Data format | Text |
Software:
| Windows, Mac, Linux | Python scripts hosted at Github (MIT Licence) |
Documentation:
| Wiki hosted at Github |
User Manual |
